1

A Widely Programmable Multiply/Divide Digital Delay Line

Year:
1990
Language:
english
File:
PDF, 584 KB
english, 1990
3

Some Algorithmic Improvements in Multi-Level Logic Minimisation

Year:
1997
Language:
english
File:
PDF, 874 KB
english, 1997
4

Implementation of a heuristic method for standard cell placement

Year:
1993
Language:
english
File:
PDF, 303 KB
english, 1993
5

Placement of Standard Cells by Multiple—Way Partitioning

Year:
1997
Language:
english
File:
PDF, 886 KB
english, 1997
6

A New Design of μ-255/ A -87. 56 CODEC Chip for Implementation with Gate Array

Year:
2000
Language:
english
File:
PDF, 1.07 MB
english, 2000